ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test

Ming-Dou Ker; Po Yen Chiu; Wuu Trong Shieh; Chun Chi Wang

doi:10.1109/TED.2016.2642042

ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test

Ming-Dou Ker, Po Yen Chiu, Wuu Trong Shieh, Chun Chi Wang

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

14 Scopus citations

Abstract

Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of ±15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.

Original language	English
Article number	7809027
Pages (from-to)	642-645
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	64
Issue number	2
DOIs	https://doi.org/10.1109/TED.2016.2642042
State	Published - Feb 2017

Keywords

Electrostatic discharge (ESD)
latchup
system-level ESD test
transmission line pulsing (TLP)

Access to Document

10.1109/TED.2016.2642042

Cite this

@article{dc99b44f0ba449d6b4dc3f869e666bf3,

title = "ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test",

abstract = "Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of ±15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.",

keywords = "Electrostatic discharge (ESD), latchup, system-level ESD test, transmission line pulsing (TLP)",

author = "Ming-Dou Ker and Chiu, {Po Yen} and Shieh, {Wuu Trong} and Wang, {Chun Chi}",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2017",

month = feb,

doi = "10.1109/TED.2016.2642042",

language = "English",

volume = "64",

pages = "642--645",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

number = "2",

}

TY - JOUR

T1 - ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test

AU - Ker, Ming-Dou

AU - Chiu, Po Yen

AU - Shieh, Wuu Trong

AU - Wang, Chun Chi

PY - 2017/2

Y1 - 2017/2

N2 - Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of ±15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.

AB - Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of ±15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.

KW - Electrostatic discharge (ESD)

KW - latchup

KW - system-level ESD test

KW - transmission line pulsing (TLP)

UR - http://www.scopus.com/inward/record.url?scp=85009892719&partnerID=8YFLogxK

U2 - 10.1109/TED.2016.2642042

DO - 10.1109/TED.2016.2642042

M3 - Article

AN - SCOPUS:85009892719

SN - 0018-9383

VL - 64

SP - 642

EP - 645

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 2

M1 - 7809027

ER -

ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this