ESD protection design for RF circuits in CMOS technology with low-c implementation

Chun Yu Lin*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    To mitigate the radio-frequency (RF) performance degradation caused by electrostatic discharge (ESD) protection device, low capacitance (low-C) design on ESD protection device is a solution. With the smaller layout area and small parasitic capacitance under the same ESD robustness, silicon-controlled rectifier (SCR) device has been used as an effective on-chip ESD protection device in RF ICs. In this paper, the modified lateral SCR (MLSCR) with the waffle layout structure is studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the minimized parasitic capacitance, the degradation on RF circuit performance can be reduced. Besides, the fast turn-on design on MLSCR without extra parasitic capacitance from the trigger circuit adding on the I/O pad is also investigated in this work.

    Original languageEnglish
    Title of host publicationSemiconductor Technology, ISTC 2008 - Proceedings of the 7th International Conference on Semiconductor Technology
    Pages70-75
    Number of pages6
    StatePublished - Mar 2008
    Event7th International Conference on Semiconductor Technology, ISTC 2008 - Shanghai, China
    Duration: 15 Mar 200817 Mar 2008

    Publication series

    NameProceedings - Electrochemical Society
    VolumePV 2008-1

    Conference

    Conference7th International Conference on Semiconductor Technology, ISTC 2008
    Country/TerritoryChina
    CityShanghai
    Period15/03/0817/03/08

    Keywords

    • ESD protection
    • Electrostatic discharge (ESD)
    • Low capacitance (low-C)
    • Radio-frequency (RF)
    • Silicon-controlled rectifier (SCR)

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