ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique

Ming-Dou Ker, Hsin Chyh Hsu

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations

    Abstract

    A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in a mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device, to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit, with the substrate-triggered technique, for a 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25 μm salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased ∼60% by this substrate-triggered design.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2003
    EditorsDong S. Ha, Richard Auletta, John Chickanosky
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages219-222
    Number of pages4
    ISBN (Electronic)0780381823, 9780780381827
    DOIs
    StatePublished - 1 Jan 2003
    EventIEEE International SOC Conference, SOCC 2003 - Portland, United States
    Duration: 17 Sep 200320 Sep 2003

    Publication series

    NameProceedings - IEEE International SOC Conference, SOCC 2003

    Conference

    ConferenceIEEE International SOC Conference, SOCC 2003
    Country/TerritoryUnited States
    CityPortland
    Period17/09/0320/09/03

    Keywords

    • Circuits
    • CMOS process
    • Electrostatic discharge
    • MOS devices
    • MOSFETs
    • Power supplies
    • Protection
    • Robustness
    • Signal design
    • Voltage

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