ESD protection design for mixed-voltage I/O interfaces - Overview

Ming Dou Ker; Kun Hsien Lin

doi:10.1109/EDSSC.2005.1635316

ESD protection design for mixed-voltage I/O interfaces - Overview

Ming Dou Ker^*, Kun Hsien Lin

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.

Original language	English
Title of host publication	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	493-498
Number of pages	6
ISBN (Print)	0780393392, 9780780393394
DOIs	https://doi.org/10.1109/EDSSC.2005.1635316
State	Published - 1 Jan 2005
Event	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon, Hong Kong Duration: 19 Dec 2005 → 21 Dec 2005

Publication series

Name	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Conference

Conference	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Country/Territory	Hong Kong
City	Howloon
Period	19/12/05 → 21/12/05

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10.1109/EDSSC.2005.1635316

Cite this

Ker, M. D., & Lin, K. H. (2005). ESD protection design for mixed-voltage I/O interfaces - Overview. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC (pp. 493-498). [1635316] (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2005.1635316

@inproceedings{b3ee779c2ff748c4bb864f422f5aad94,

title = "ESD protection design for mixed-voltage I/O interfaces - Overview",

abstract = "Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.",

author = "Ker, {Ming Dou} and Lin, {Kun Hsien}",

year = "2005",

month = jan,

day = "1",

doi = "10.1109/EDSSC.2005.1635316",

language = "English",

isbn = "0780393392",

series = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "493--498",

booktitle = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

address = "United States",

note = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC ; Conference date: 19-12-2005 Through 21-12-2005",

}

Ker, MD & Lin, KH 2005, ESD protection design for mixed-voltage I/O interfaces - Overview. in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC., 1635316, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Institute of Electrical and Electronics Engineers Inc., pp. 493-498, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Howloon, Hong Kong, 19/12/05. https://doi.org/10.1109/EDSSC.2005.1635316

ESD protection design for mixed-voltage I/O interfaces - Overview. / Ker, Ming Dou; Lin, Kun Hsien.
2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. Institute of Electrical and Electronics Engineers Inc., 2005. p. 493-498 1635316 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ker, Ming Dou

AU - Lin, Kun Hsien

PY - 2005/1/1

Y1 - 2005/1/1

N2 - Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.

AB - Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.

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U2 - 10.1109/EDSSC.2005.1635316

DO - 10.1109/EDSSC.2005.1635316

M3 - Conference contribution

AN - SCOPUS:43549119002

SN - 0780393392

SN - 9780780393394

T3 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

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BT - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Y2 - 19 December 2005 through 21 December 2005

ER -

ESD protection design for mixed-voltage I/O interfaces - Overview

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