ESD protection design for low trigger voltage and high latch-up immunity

Jen Chou Tseng; Chung Ti Hsu; Chia Ku Tsai; Yu Ching Liao; Ming-Dou Ker

doi:10.1109/IPFA.2010.5532307

ESD protection design for low trigger voltage and high latch-up immunity

Jen Chou Tseng^*, Chung Ti Hsu, Chia Ku Tsai, Yu Ching Liao, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

An embedded silicon-controlled rectifier (SCR) protection structure is proposed with a compatible CMOS layout. It first turns on like a gate-coupled NMOSFET, and then provides second-snapback conduction by a parasitic SCR. As compared with a conventional gate-ground NMOS transistor, the trigger voltage and the human body mode (HBM) test immunity are both greatly improved. Also, this cell is latch-up resistant, both the holding voltage and the turn-on current are adjustable and greatly raised than those of a conventional SCR device.

Original language	English
Title of host publication	IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
DOIs	https://doi.org/10.1109/IPFA.2010.5532307
State	Published - 15 Sep 2010
Event	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore Duration: 5 Jul 2010 → 9 Jul 2010

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010
Country/Territory	Singapore
City	Singapore
Period	5/07/10 → 9/07/10

Keywords

Device reliability
ESD
Latch-up

Access to Document

10.1109/IPFA.2010.5532307

Cite this

Tseng, J. C., Hsu, C. T., Tsai, C. K., Liao, Y. C., & Ker, M-D. (2010). ESD protection design for low trigger voltage and high latch-up immunity. In IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits [5532307] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2010.5532307

@inproceedings{ab52b7e658df49628bc92f16691b0b12,

title = "ESD protection design for low trigger voltage and high latch-up immunity",

abstract = "An embedded silicon-controlled rectifier (SCR) protection structure is proposed with a compatible CMOS layout. It first turns on like a gate-coupled NMOSFET, and then provides second-snapback conduction by a parasitic SCR. As compared with a conventional gate-ground NMOS transistor, the trigger voltage and the human body mode (HBM) test immunity are both greatly improved. Also, this cell is latch-up resistant, both the holding voltage and the turn-on current are adjustable and greatly raised than those of a conventional SCR device.",

keywords = "Device reliability, ESD, Latch-up",

author = "Tseng, {Jen Chou} and Hsu, {Chung Ti} and Tsai, {Chia Ku} and Liao, {Yu Ching} and Ming-Dou Ker",

year = "2010",

month = sep,

day = "15",

doi = "10.1109/IPFA.2010.5532307",

language = "English",

isbn = "9781424455973",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

booktitle = "IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits",

note = "17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 ; Conference date: 05-07-2010 Through 09-07-2010",

}

Tseng, JC, Hsu, CT, Tsai, CK, Liao, YC & Ker, M-D 2010, ESD protection design for low trigger voltage and high latch-up immunity. in IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits., 5532307, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010, Singapore, Singapore, 5/07/10. https://doi.org/10.1109/IPFA.2010.5532307

ESD protection design for low trigger voltage and high latch-up immunity. / Tseng, Jen Chou; Hsu, Chung Ti; Tsai, Chia Ku et al.
IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits. 2010. 5532307 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ESD protection design for low trigger voltage and high latch-up immunity

AU - Tseng, Jen Chou

AU - Hsu, Chung Ti

AU - Tsai, Chia Ku

AU - Liao, Yu Ching

AU - Ker, Ming-Dou

PY - 2010/9/15

Y1 - 2010/9/15

N2 - An embedded silicon-controlled rectifier (SCR) protection structure is proposed with a compatible CMOS layout. It first turns on like a gate-coupled NMOSFET, and then provides second-snapback conduction by a parasitic SCR. As compared with a conventional gate-ground NMOS transistor, the trigger voltage and the human body mode (HBM) test immunity are both greatly improved. Also, this cell is latch-up resistant, both the holding voltage and the turn-on current are adjustable and greatly raised than those of a conventional SCR device.

AB - An embedded silicon-controlled rectifier (SCR) protection structure is proposed with a compatible CMOS layout. It first turns on like a gate-coupled NMOSFET, and then provides second-snapback conduction by a parasitic SCR. As compared with a conventional gate-ground NMOS transistor, the trigger voltage and the human body mode (HBM) test immunity are both greatly improved. Also, this cell is latch-up resistant, both the holding voltage and the turn-on current are adjustable and greatly raised than those of a conventional SCR device.

KW - Device reliability

KW - ESD

KW - Latch-up

UR - http://www.scopus.com/inward/record.url?scp=77956441363&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2010.5532307

DO - 10.1109/IPFA.2010.5532307

M3 - Conference contribution

AN - SCOPUS:77956441363

SN - 9781424455973

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

BT - IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits

T2 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010

Y2 - 5 July 2010 through 9 July 2010

ER -

Tseng JC, Hsu CT, Tsai CK, Liao YC, Ker M-D. ESD protection design for low trigger voltage and high latch-up immunity. In IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits. 2010. 5532307. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2010.5532307

ESD protection design for low trigger voltage and high latch-up immunity

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