ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure

Kun Hsien Lin; Ming-Dou Ker

doi:10.1109/ISCAS.2005.1464805

ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of I/O cell.

Original language	English
Article number	1464805
Pages (from-to)	1182-1185
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464805
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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@article{465e09b4b37f4096b59c7fec31198ace,

title = "ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure",

abstract = "This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of I/O cell.",

author = "Lin, {Kun Hsien} and Ming-Dou Ker",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ISCAS.2005.1464805",

language = "English",

pages = "1182--1185",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 23-05-2005 Through 26-05-2005",

}

TY - JOUR

T1 - ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure

AU - Lin, Kun Hsien

AU - Ker, Ming-Dou

PY - 2005/12/1

Y1 - 2005/12/1

N2 - This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of I/O cell.

AB - This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of I/O cell.

UR - http://www.scopus.com/inward/record.url?scp=67649095486&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2005.1464805

DO - 10.1109/ISCAS.2005.1464805

M3 - Conference article

AN - SCOPUS:67649095486

SN - 0271-4310

SP - 1182

EP - 1185

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1464805

Y2 - 23 May 2005 through 26 May 2005

ER -

ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure

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