ESD protection design for IC with power-down-mode operation

Ming-Dou Ker*, Kun Hsien Lin

*Corresponding author for this work

    Research output: Contribution to journalConference articlepeer-review

    3 Scopus citations

    Abstract

    A new ESD protection design for IC with power-down operation is proposed. By adding a VDD ESD bus line and diodes into the new ESD protection scheme, the leakage current from I/O pin to VDD power line can be blocked to avoid malfunction under the power-down-mode operating condition. Under normal circuit operating condition, the proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. Power-rail ESD clamp circuits between the VDD/VSS power lines and VDD ESD bus line are used to achieve whole-chip ESD protection design. From the experimental results, the human-body-model (HBM) ESD level of the new proposed ESD protection schemes can be greater than 7.5kV in a 0.35-μm silicided CMOS process.

    Original languageEnglish
    Pages (from-to)II717-II720
    JournalProceedings - IEEE International Symposium on Circuits and Systems
    Volume2
    DOIs
    StatePublished - 2004
    Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
    Duration: 23 May 200426 May 2004

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