ESD protection design for IC with power-down-mode operation

Ming-Dou Ker; Kun Hsien Lin

doi:10.1109/ISCAS.2004.1329372

ESD protection design for IC with power-down-mode operation

Ming-Dou Ker^*, Kun Hsien Lin

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

A new ESD protection design for IC with power-down operation is proposed. By adding a VDD ESD bus line and diodes into the new ESD protection scheme, the leakage current from I/O pin to VDD power line can be blocked to avoid malfunction under the power-down-mode operating condition. Under normal circuit operating condition, the proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. Power-rail ESD clamp circuits between the VDD/VSS power lines and VDD ESD bus line are used to achieve whole-chip ESD protection design. From the experimental results, the human-body-model (HBM) ESD level of the new proposed ESD protection schemes can be greater than 7.5kV in a 0.35-μm silicided CMOS process.

Original language	English
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/ISCAS.2004.1329372
State	Published - 7 Sep 2004
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004

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@article{b40b880c6830469f86a6b9206d57267a,

title = "ESD protection design for IC with power-down-mode operation",

abstract = "A new ESD protection design for IC with power-down operation is proposed. By adding a VDD ESD bus line and diodes into the new ESD protection scheme, the leakage current from I/O pin to VDD power line can be blocked to avoid malfunction under the power-down-mode operating condition. Under normal circuit operating condition, the proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. Power-rail ESD clamp circuits between the VDD/VSS power lines and VDD ESD bus line are used to achieve whole-chip ESD protection design. From the experimental results, the human-body-model (HBM) ESD level of the new proposed ESD protection schemes can be greater than 7.5kV in a 0.35-μm silicided CMOS process.",

author = "Ming-Dou Ker and Lin, {Kun Hsien}",

year = "2004",

month = sep,

day = "7",

doi = "10.1109/ISCAS.2004.1329372",

language = "English",

volume = "2",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 23-05-2004 Through 26-05-2004",

}

TY - JOUR

T1 - ESD protection design for IC with power-down-mode operation

AU - Ker, Ming-Dou

AU - Lin, Kun Hsien

PY - 2004/9/7

Y1 - 2004/9/7

N2 - A new ESD protection design for IC with power-down operation is proposed. By adding a VDD ESD bus line and diodes into the new ESD protection scheme, the leakage current from I/O pin to VDD power line can be blocked to avoid malfunction under the power-down-mode operating condition. Under normal circuit operating condition, the proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. Power-rail ESD clamp circuits between the VDD/VSS power lines and VDD ESD bus line are used to achieve whole-chip ESD protection design. From the experimental results, the human-body-model (HBM) ESD level of the new proposed ESD protection schemes can be greater than 7.5kV in a 0.35-μm silicided CMOS process.

AB - A new ESD protection design for IC with power-down operation is proposed. By adding a VDD ESD bus line and diodes into the new ESD protection scheme, the leakage current from I/O pin to VDD power line can be blocked to avoid malfunction under the power-down-mode operating condition. Under normal circuit operating condition, the proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. Power-rail ESD clamp circuits between the VDD/VSS power lines and VDD ESD bus line are used to achieve whole-chip ESD protection design. From the experimental results, the human-body-model (HBM) ESD level of the new proposed ESD protection schemes can be greater than 7.5kV in a 0.35-μm silicided CMOS process.

UR - http://www.scopus.com/inward/record.url?scp=3843087659&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2004.1329372

DO - 10.1109/ISCAS.2004.1329372

M3 - Conference article

AN - SCOPUS:3843087659

SN - 0271-4310

VL - 2

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 23 May 2004 through 26 May 2004

ER -

ESD protection design for IC with power-down-mode operation

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