ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process

Ming-Dou Ker; Che Hao Chuang

doi:10.1109/IPFA.2004.1345600

ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process

Ming-Dou Ker^*, Che Hao Chuang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

4 Scopus citations

Abstract

ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.

Original language	English
Pages	217-220
Number of pages	4
DOIs	https://doi.org/10.1109/IPFA.2004.1345600
State	Published - 1 Dec 2004
Event	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan Duration: 5 Jul 2004 → 8 Jul 2004

Conference

Conference	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
Country/Territory	Taiwan
Period	5/07/04 → 8/07/04

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10.1109/IPFA.2004.1345600

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title = "ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process",

abstract = "ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.",

author = "Ming-Dou Ker and Chuang, {Che Hao}",

year = "2004",

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doi = "10.1109/IPFA.2004.1345600",

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Ker, M-D & Chuang, CH 2004, 'ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process', Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan, 5/07/04 - 8/07/04 pp. 217-220. https://doi.org/10.1109/IPFA.2004.1345600

ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process. / Ker, Ming-Dou; Chuang, Che Hao.
2004. 217-220 Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan.

Research output: Contribution to conference › Paper › peer-review

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T1 - ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process

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N2 - ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.

AB - ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.

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ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process

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