ESD protection design for high-speed applications in CMOS technology

Jie Ting Chen; Chun Yu Lin; Rong Kun Chang; Ming Dou Ker; Tzu Chien Tzeng; Tzu Chiang Lin

doi:10.1109/MWSCAS.2016.7870016

ESD protection design for high-speed applications in CMOS technology

Jie Ting Chen, Chun Yu Lin, Rong Kun Chang, Ming Dou Ker, Tzu Chien Tzeng, Tzu Chiang Lin

Institute of Photonic System

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.

Original language	English
Title of host publication	2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509009169
DOIs	https://doi.org/10.1109/MWSCAS.2016.7870016
State	Published - 2 Jul 2016
Event	59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 - Abu Dhabi, United Arab Emirates Duration: 16 Oct 2016 → 19 Oct 2016

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	0
ISSN (Print)	1548-3746

Conference

Conference	59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	16/10/16 → 19/10/16

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10.1109/MWSCAS.2016.7870016

Cite this

Chen, J. T., Lin, C. Y., Chang, R. K., Ker, M. D., Tzeng, T. C., & Lin, T. C. (2016). ESD protection design for high-speed applications in CMOS technology. In 2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016 Article 7870016 (Midwest Symposium on Circuits and Systems; Vol. 0). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2016.7870016

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title = "ESD protection design for high-speed applications in CMOS technology",

abstract = "To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.",

author = "Chen, {Jie Ting} and Lin, {Chun Yu} and Chang, {Rong Kun} and Ker, {Ming Dou} and Tzeng, {Tzu Chien} and Lin, {Tzu Chiang}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 ; Conference date: 16-10-2016 Through 19-10-2016",

year = "2016",

month = jul,

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doi = "10.1109/MWSCAS.2016.7870016",

language = "English",

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Chen, JT, Lin, CY, Chang, RK, Ker, MD, Tzeng, TC & Lin, TC 2016, ESD protection design for high-speed applications in CMOS technology. in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016., 7870016, Midwest Symposium on Circuits and Systems, vol. 0, Institute of Electrical and Electronics Engineers Inc., 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, 16/10/16. https://doi.org/10.1109/MWSCAS.2016.7870016

ESD protection design for high-speed applications in CMOS technology. / Chen, Jie Ting; Lin, Chun Yu; Chang, Rong Kun et al.
2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7870016 (Midwest Symposium on Circuits and Systems; Vol. 0).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lin, Chun Yu

AU - Chang, Rong Kun

AU - Ker, Ming Dou

AU - Tzeng, Tzu Chien

AU - Lin, Tzu Chiang

PY - 2016/7/2

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N2 - To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.

AB - To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.

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DO - 10.1109/MWSCAS.2016.7870016

M3 - Conference contribution

AN - SCOPUS:85015877405

T3 - Midwest Symposium on Circuits and Systems

BT - 2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016

Y2 - 16 October 2016 through 19 October 2016

ER -

ESD protection design for high-speed applications in CMOS technology

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