ESD Protection Design for Fan-Out Panel-Level Packaging

Chun Yu Lin, Chia You Hsieh, Zih Jyun Dai, Yu Hsuan Lai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

With a new concept of hetero-integration by combining display and functional redistribution layer (RDL) technologies, the fan-out panel-level package (FOPLP) technology with ESD protection design is studied in this work. The proposed ESD protection circuits in RDL are realized by low temperature poly silicon thin film transistor, and the circuits are used to protect a CMOS inverter. The ESD protection circuits for FOPLP applications are verified in this work.

Original languageEnglish
Title of host publicationInternational EOS/ESD Symposium on Design and System, IEDS 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781585373383
StatePublished - 2022
Event2nd Annual International EOS/ESD Symposium on Design and System, IEDS 2022 - Virtual, Online, China
Duration: 9 Nov 202211 Nov 2022

Publication series

NameInternational EOS/ESD Symposium on Design and System, IEDS 2022

Conference

Conference2nd Annual International EOS/ESD Symposium on Design and System, IEDS 2022
Country/TerritoryChina
CityVirtual, Online
Period9/11/2211/11/22

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