ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces

Wei Jen Chang; Ming-Dou Ker

doi:10.1109/RME.2006.1689957

ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces

Wei Jen Chang^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/ PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces.

Original language	English
Title of host publication	PRIME 2006
Subtitle of host publication	2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings
Pages	305-308
Number of pages	4
DOIs	https://doi.org/10.1109/RME.2006.1689957
State	Published - 1 Dec 2006
Event	PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Otranto, Italy Duration: 12 Jun 2006 → 15 Jun 2006

Publication series

Name	PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings

Conference

Conference	PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics
Country/Territory	Italy
City	Otranto
Period	12/06/06 → 15/06/06

Access to Document

10.1109/RME.2006.1689957

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Chang, W. J., & Ker, M.-D. (2006). ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces. In PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings (pp. 305-308). Article 1689957 (PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings). https://doi.org/10.1109/RME.2006.1689957

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title = "ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces",

abstract = "With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/ PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces.",

author = "Chang, {Wei Jen} and Ming-Dou Ker",

year = "2006",

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day = "1",

doi = "10.1109/RME.2006.1689957",

language = "English",

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Chang, WJ & Ker, M-D 2006, ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces. in PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings., 1689957, PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings, pp. 305-308, PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, 12/06/06. https://doi.org/10.1109/RME.2006.1689957

ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces. / Chang, Wei Jen; Ker, Ming-Dou.
PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings. 2006. p. 305-308 1689957 (PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ker, Ming-Dou

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N2 - With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/ PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces.

AB - With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/ PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces.

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ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces

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