ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffers with 3×VDD input tolerance

Ming-Dou Ker; Chang Tzu Wang

doi:10.1109/ASSCC.2006.357907

ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffers with 3×VDD input tolerance

Ming-Dou Ker^*, Chang Tzu Wang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

7 Scopus citations

Abstract

A new electrostatic discharge (ESD) protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-μm CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3×VDD input tolerance.

Original language	English
Pages	287-290
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357907
State	Published - 1 Dec 2006
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 Nov 2006 → 15 Nov 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357907

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@conference{4ec166945ed0465ba2cb1a9cbd2e5307,

title = "ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffers with 3×VDD input tolerance",

abstract = "A new electrostatic discharge (ESD) protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-μm CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3×VDD input tolerance.",

author = "Ming-Dou Ker and Wang, {Chang Tzu}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2006.357907",

language = "English",

pages = "287--290",

note = "2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 ; Conference date: 13-11-2006 Through 15-11-2006",

}

TY - CONF

T1 - ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffers with 3×VDD input tolerance

AU - Ker, Ming-Dou

AU - Wang, Chang Tzu

PY - 2006/12/1

Y1 - 2006/12/1

N2 - A new electrostatic discharge (ESD) protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-μm CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3×VDD input tolerance.

AB - A new electrostatic discharge (ESD) protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-μm CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3×VDD input tolerance.

UR - http://www.scopus.com/inward/record.url?scp=34250876938&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2006.357907

DO - 10.1109/ASSCC.2006.357907

M3 - Paper

AN - SCOPUS:34250876938

SP - 287

EP - 290

T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Y2 - 13 November 2006 through 15 November 2006

ER -

ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffers with 3×VDD input tolerance

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