ESD protection design and verification in a 0.35-μm CMOS ASIC library

Ming-Dou Ker; Hsin Chin Jiang; Jeng Jie Peng

doi:10.1109/ASIC.1999.806516

ESD protection design and verification in a 0.35-μm CMOS ASIC library

Ming-Dou Ker, Hsin Chin Jiang, Jeng Jie Peng

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-μm silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-μm CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-μm CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.

Original language	English
Title of host publication	Proceedings - 12th Annual IEEE International ASIC/SOC Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	262-266
Number of pages	5
ISBN (Electronic)	0780356322, 9780780356320
DOIs	https://doi.org/10.1109/ASIC.1999.806516
State	Published - 1 Jan 1999
Event	12th Annual IEEE International ASIC/SOC Conference - Washington, United States Duration: 15 Sep 1999 → 18 Sep 1999

Publication series

Name	Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Conference

Conference	12th Annual IEEE International ASIC/SOC Conference
Country/Territory	United States
City	Washington
Period	15/09/99 → 18/09/99

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10.1109/ASIC.1999.806516

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Ker, M.-D., Jiang, H. C., & Peng, J. J. (1999). ESD protection design and verification in a 0.35-μm CMOS ASIC library. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 262-266). Article 806516 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806516

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title = "ESD protection design and verification in a 0.35-μm CMOS ASIC library",

abstract = "In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-μm silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-μm CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-μm CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.",

author = "Ming-Dou Ker and Jiang, {Hsin Chin} and Peng, {Jeng Jie}",

year = "1999",

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doi = "10.1109/ASIC.1999.806516",

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note = "12th Annual IEEE International ASIC/SOC Conference ; Conference date: 15-09-1999 Through 18-09-1999",

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Ker, M-D, Jiang, HC & Peng, JJ 1999, ESD protection design and verification in a 0.35-μm CMOS ASIC library. in Proceedings - 12th Annual IEEE International ASIC/SOC Conference., 806516, Proceedings - 12th Annual IEEE International ASIC/SOC Conference, Institute of Electrical and Electronics Engineers Inc., pp. 262-266, 12th Annual IEEE International ASIC/SOC Conference, Washington, United States, 15/09/99. https://doi.org/10.1109/ASIC.1999.806516

ESD protection design and verification in a 0.35-μm CMOS ASIC library. / Ker, Ming-Dou; Jiang, Hsin Chin; Peng, Jeng Jie.
Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., 1999. p. 262-266 806516 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-μm silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-μm CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-μm CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.

AB - In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-μm silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-μm CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-μm CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.

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ESD protection design and verification in a 0.35-μm CMOS ASIC library

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