ESD protection consideration in nanoscale CMOS technology

Ming-Dou Ker; Chun Yu Lin

doi:10.1109/NANO.2011.6144345

ESD protection consideration in nanoscale CMOS technology

Ming-Dou Ker^*, Chun Yu Lin

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.

Original language	English
Title of host publication	2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Pages	720-723
Number of pages	4
DOIs	https://doi.org/10.1109/NANO.2011.6144345
State	Published - 1 Dec 2011
Event	2011 11th IEEE International Conference on Nanotechnology, NANO 2011 - Portland, OR, United States Duration: 15 Aug 2011 → 19 Aug 2011

Publication series

Name	Proceedings of the IEEE Conference on Nanotechnology
ISSN (Print)	1944-9399
ISSN (Electronic)	1944-9380

Conference

Conference	2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Country/Territory	United States
City	Portland, OR
Period	15/08/11 → 19/08/11

Keywords

CMOS
electrostatic discharge (ESD)
on-chip ESD protection

Access to Document

10.1109/NANO.2011.6144345

Cite this

@inproceedings{805824dcb17644dd86cca79e2f3d8cbd,

title = "ESD protection consideration in nanoscale CMOS technology",

abstract = "The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.",

keywords = "CMOS, electrostatic discharge (ESD), on-chip ESD protection",

author = "Ming-Dou Ker and Lin, {Chun Yu}",

year = "2011",

month = dec,

day = "1",

doi = "10.1109/NANO.2011.6144345",

language = "English",

isbn = "9781457715143",

series = "Proceedings of the IEEE Conference on Nanotechnology",

pages = "720--723",

booktitle = "2011 11th IEEE International Conference on Nanotechnology, NANO 2011",

note = "2011 11th IEEE International Conference on Nanotechnology, NANO 2011 ; Conference date: 15-08-2011 Through 19-08-2011",

}

Ker, M-D & Lin, CY 2011, ESD protection consideration in nanoscale CMOS technology. in 2011 11th IEEE International Conference on Nanotechnology, NANO 2011., 6144345, Proceedings of the IEEE Conference on Nanotechnology, pp. 720-723, 2011 11th IEEE International Conference on Nanotechnology, NANO 2011, Portland, OR, United States, 15/08/11. https://doi.org/10.1109/NANO.2011.6144345

TY - GEN

T1 - ESD protection consideration in nanoscale CMOS technology

AU - Ker, Ming-Dou

AU - Lin, Chun Yu

PY - 2011/12/1

Y1 - 2011/12/1

N2 - The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.

AB - The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.

KW - CMOS

KW - electrostatic discharge (ESD)

KW - on-chip ESD protection

UR - http://www.scopus.com/inward/record.url?scp=84858969202&partnerID=8YFLogxK

U2 - 10.1109/NANO.2011.6144345

DO - 10.1109/NANO.2011.6144345

M3 - Conference contribution

AN - SCOPUS:84858969202

SN - 9781457715143

T3 - Proceedings of the IEEE Conference on Nanotechnology

SP - 720

EP - 723

BT - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011

T2 - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011

Y2 - 15 August 2011 through 19 August 2011

ER -

ESD protection consideration in nanoscale CMOS technology

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this