ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup

Ming-Dou Ker; Che Lun Hsu; Wen Yi Chen

doi:10.1109/ISCAS.2010.5537378

ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup

Ming-Dou Ker^*, Che Lun Hsu, Wen Yi Chen

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-μm 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	989-992
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537378
State	Published - 31 Aug 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 30 May 2010 → 2 Jun 2010

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	30/05/10 → 2/06/10

Access to Document

10.1109/ISCAS.2010.5537378

Cite this

Ker, M-D., Hsu, C. L., & Chen, W. Y. (2010). ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 989-992). [5537378] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537378

Ker, Ming-Dou ; Hsu, Che Lun ; Chen, Wen Yi. / ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 989-992 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

@inproceedings{bee0a9bc7a7d40b1901d255477bcc334,

title = "ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup",

abstract = "With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-μm 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.",

author = "Ming-Dou Ker and Hsu, {Che Lun} and Chen, {Wen Yi}",

year = "2010",

month = aug,

day = "31",

doi = "10.1109/ISCAS.2010.5537378",

language = "English",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

pages = "989--992",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

Ker, M-D, Hsu, CL & Chen, WY 2010, ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537378, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 989-992, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 30/05/10. https://doi.org/10.1109/ISCAS.2010.5537378

ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. / Ker, Ming-Dou; Hsu, Che Lun; Chen, Wen Yi.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 989-992 5537378 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup

AU - Ker, Ming-Dou

AU - Hsu, Che Lun

AU - Chen, Wen Yi

PY - 2010/8/31

Y1 - 2010/8/31

N2 - With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-μm 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.

AB - With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-μm 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.

UR - http://www.scopus.com/inward/record.url?scp=77955996353&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5537378

DO - 10.1109/ISCAS.2010.5537378

M3 - Conference contribution

AN - SCOPUS:77955996353

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 989

EP - 992

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

Ker M-D, Hsu CL, Chen WY. ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 989-992. 5537378. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537378

ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this