@inproceedings{0f7dc82f09ce40d1ab441c80cbe676c7,
title = "ESD-induced latchup-like failure in a touch panel control IC",
abstract = "With on-chip ESD protection design, the I/O pins of a touch panel control IC can pass the chip-level ESD tests of HBM 4kV and MM 400V. However, such a touch panel control IC mounted onto a display panel suffered the latchup-like failure after the system-level ESD zapping in the air-discharge mode. Some high-voltage power pin began to generate a large leakage current after the system-level ESD test, which demonstrated a symptom of latchup failure. By failure analyses with TLP-measurement, EMMI, and SEM, the root cause has been found on the power-rail ESD clamp circuit of the high-voltage power pin. The holding voltage of the power-rail ESD clamp circuit in the high-voltage power pin, that was lower than its normal operating voltage, caused such a latchup-like failure. Some modified solutions to rescue this latchup-like failure in the touch panel control IC are presented.",
author = "Ming-Dou Ker and Chiu, {Po Yen} and Shieh, {Wuu Trong} and Wang, {Chun Chi}",
year = "2017",
month = oct,
day = "5",
doi = "10.1109/IPFA.2017.8060061",
language = "English",
series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--5",
booktitle = "24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017",
address = "United States",
note = "null ; Conference date: 04-07-2017 Through 07-07-2017",
}