ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Ming-Dou Ker; C. H. Chuang

doi:10.1109/IPFA.2001.941461

ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Ming-Dou Ker^*, C. H. Chuang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

23 Scopus citations

Abstract

The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

Original language	English
Pages	85-90
Number of pages	6
DOIs	https://doi.org/10.1109/IPFA.2001.941461
State	Published - 13 Jul 2001
Event	8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore Duration: 9 Jul 2001 → 13 Jul 2001

Conference

Conference	8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
Country/Territory	Singapore
City	Singapure
Period	9/07/01 → 13/07/01

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10.1109/IPFA.2001.941461

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title = "ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration",

abstract = "The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.",

author = "Ming-Dou Ker and Chuang, {C. H.}",

year = "2001",

month = jul,

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doi = "10.1109/IPFA.2001.941461",

language = "English",

pages = "85--90",

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T1 - ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

AU - Ker, Ming-Dou

AU - Chuang, C. H.

PY - 2001/7/13

Y1 - 2001/7/13

N2 - The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

AB - The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

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U2 - 10.1109/IPFA.2001.941461

DO - 10.1109/IPFA.2001.941461

M3 - Paper

AN - SCOPUS:0034823704

SP - 85

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T2 - 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)

Y2 - 9 July 2001 through 13 July 2001

ER -

ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Abstract

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