Erratum: A 15-Bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (IEEE Journal of Solid-state Circuits)

Hung Chih Liu*, Zwei Mei Lee, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalComment/debate

Original languageEnglish
Number of pages1
JournalIEEE Journal of Solid-State Circuits
Issue number11
StatePublished - 1 Nov 2005

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