EOS Failure in Low-Voltage Core Circuits during Latch-up Test at I/O Pins

Chen Wei Hsu, Ming Dou Ker, Ping Lin Chung, Chin Tung Cheng, Chih Ping Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The occurrence of electrical overstress (EOS) failure in low-voltage core circuits resulting from latch-up test at the I/O pins was investigated, where a specific commercial IC product equipped with on-chip low-dropout regulator (LDO). Through failure analysis experiments, the root cause of EOS failures is identified to the abnormal LDO output voltage during latch-up test. In this work, a modified design featuring a deep n-well (DNW) beneath the NMOS region is proposed to mitigate EOS issue by enhancing electron absorption. Additionally, compensation network configurations are explored to explain the abnormal LDO operation. The experimental results from test chip have validated the effectiveness of the proposed modifications, emphasizing the importance of proactive measures in mitigating EOS failures.

Original languageEnglish
Title of host publicationISTFA 2024
Subtitle of host publicationProceedings from the 50th International Symposium for Testing and Failure Analysis Conference
PublisherASM International
Pages42-46
Number of pages5
ISBN (Electronic)9781627084918
DOIs
StatePublished - 2024
Event50th International Symposium for Testing and Failure Analysis Conference, ISTFA 2024 - San Diego, United States
Duration: 28 Oct 20241 Nov 2024

Publication series

NameConference Proceedings from the International Symposium for Testing and Failure Analysis
Volume2024-October
ISSN (Print)0890-1740

Conference

Conference50th International Symposium for Testing and Failure Analysis Conference, ISTFA 2024
Country/TerritoryUnited States
CitySan Diego
Period28/10/241/11/24

Keywords

  • deep n-well
  • electrical overstress (EOS)
  • latch-up test
  • low-dropout regulator

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