TY - GEN
T1 - Enhancement in Capacitance and Transconductance in 90 nm nFETs with HfO2-ZrO2Superlattice Gate Stack for Energy-efficient Cryo-CMOS
AU - Li, W.
AU - Wang, L. C.
AU - Cheema, S. S.
AU - Shanker, N.
AU - Hu, C.
AU - Salahuddin, S.
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - We show from cryogenic RF characterization that the negative-capacitance (NC) mixed-ferroic HfO2-ZrO2 superlattice (HZH) gate stack [1] on SOI nFETs provides dispersion-free capacitance enhancement (< 8 Å EOT) over regular HfO2 high-k gate stack up to 40 GHz all the way down to 77 K. Furthermore, the electron injection velocity is unaffected by the capacitance enhancement and shows a 40% increase at 77 K, leading to a record-high intrinsic transconductance of 2.03 mS/ mum from L-{g}=90 nm SOI nFETs, which is 19% higher than from regular HfO2 gate stack. By elaborate analysis of the DC characteristics with a newly modified 2-valley Cryo-MVS model, we show that degeneracy statistics is important for the thermal velocity at low temperatures and can be harnessed to boost Ion with EOT reduction. Projected I-{on}/V-{dd} from 5-nm nanosheet nFETs with L-{g}=16 nm can reach 1 mS/ mum under V-{dd}=0.2V with a 6.5 { AA} EOT demonstrated previously from the HZH gate stack [1], suggesting the low EOT NC gate stack as an attractive technology booster for energy-efficient cryo-CMOS.
AB - We show from cryogenic RF characterization that the negative-capacitance (NC) mixed-ferroic HfO2-ZrO2 superlattice (HZH) gate stack [1] on SOI nFETs provides dispersion-free capacitance enhancement (< 8 Å EOT) over regular HfO2 high-k gate stack up to 40 GHz all the way down to 77 K. Furthermore, the electron injection velocity is unaffected by the capacitance enhancement and shows a 40% increase at 77 K, leading to a record-high intrinsic transconductance of 2.03 mS/ mum from L-{g}=90 nm SOI nFETs, which is 19% higher than from regular HfO2 gate stack. By elaborate analysis of the DC characteristics with a newly modified 2-valley Cryo-MVS model, we show that degeneracy statistics is important for the thermal velocity at low temperatures and can be harnessed to boost Ion with EOT reduction. Projected I-{on}/V-{dd} from 5-nm nanosheet nFETs with L-{g}=16 nm can reach 1 mS/ mum under V-{dd}=0.2V with a 6.5 { AA} EOT demonstrated previously from the HZH gate stack [1], suggesting the low EOT NC gate stack as an attractive technology booster for energy-efficient cryo-CMOS.
UR - http://www.scopus.com/inward/record.url?scp=85147522225&partnerID=8YFLogxK
U2 - 10.1109/IEDM45625.2022.10019496
DO - 10.1109/IEDM45625.2022.10019496
M3 - Conference contribution
AN - SCOPUS:85147522225
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 2231
EP - 2234
BT - 2022 International Electron Devices Meeting, IEDM 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 International Electron Devices Meeting, IEDM 2022
Y2 - 3 December 2022 through 7 December 2022
ER -