Embedded TCP/IP Controller for a RISC-V SoC

Computer Science

• System-on-Chip 100%
• Computer Hardware 100%
• Open Source 50%
• Experimental Result 50%
• Control Algorithm 50%
• High Throughput 50%
• Packet Transmission 50%
• Processor Core 50%
• Software Implementation 50%
• Packet Delay 50%
• Software Layer 50%
• Application Processor 50%
• Development Board 50%
• Control Behavior 50%
• Real-Time Operating System 50%
• Field Programmable Gate Arrays 50%

Keyphrases

• TCPIP 100%
• PI Controller 100%
• RISC-V 100%
• Proposed Architecture 33%
• Network Modules 33%
• Low Latency 16%
• Control Algorithm 16%
• IP Packet 16%
• IP Networks 16%
• High-throughput 16%
• Processor Core 16%
• Software Implementation 16%
• Packet Transmission 16%
• Controlling Behavior 16%
• Software Layer 16%
• Hardwired 16%
• Real-time Operating System 16%
• Xilinx FPGA 16%
• Development Board 16%
• Application-specific Processors 16%
• Low-power Processors 16%
• End-to-end Packet Delay 16%
• OS Kernel 16%
• Complex Control 16%
• Network Stack 16%
• Software Network 16%
• IP Control 16%
• FreeRTOS 16%