Embedded TCP/IP Controller for a RISC-V SoC

Chun Jen Tsai, Yi De Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


In this paper, we present the design of an open-source RISC-V application processor with an embedded TCP/IP network module. Traditionally, the TCP/IP stack is a software layer of the OS kernel due to its complex control behavior. However, previous studies show that a hardwired logic can perform the TCP/IP control algorithms much more efficiently than a software implementation. However, to allow a processor to invoke a hardware TCP/IP logic efficiently is not a trivial task. This paper proposes an efficient interface logic between the processor core and the hardware TCP/IP stack through user-defined RISC-V instructions. The proposed architecture is implemented and verified on a Xilinx FPGA development board. Experimental results show that the average end-to-end packet delay can be reduced by up to 99% using the proposed network module when compared against the software network stack under the FreeRTOS real-time operating system. Therefore, the proposed architecture can be very useful for deeply-embedded IOT devices where a low-power processor can be used to handle low-latency high throughput IP packet transmissions.

Original languageEnglish
Title of host publicationProceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022
PublisherIEEE Computer Society
ISBN (Electronic)9781665490054
StatePublished - 2022
Event30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022 - Patras, Greece
Duration: 3 Oct 20225 Oct 2022

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440


Conference30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022


  • FPGA
  • RISC-V SoC design
  • TCP/IP hardware
  • application-specific ISA
  • application-specific processors
  • processor architecture


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