TY - GEN
T1 - Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach
AU - Su, Pin
AU - You, Wei Xiang
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.
AB - Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.
UR - http://www.scopus.com/inward/record.url?scp=85081064181&partnerID=8YFLogxK
U2 - 10.1109/IEDM19573.2019.8993444
DO - 10.1109/IEDM19573.2019.8993444
M3 - Conference contribution
AN - SCOPUS:85081064181
T3 - Technical Digest - International Electron Devices Meeting, IEDM
BT - 2019 IEEE International Electron Devices Meeting, IEDM 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Y2 - 7 December 2019 through 11 December 2019
ER -