Electrostatic discharge protection under pad design for copper-low-K VLSI circuits

Jam Wem Lee; Yi-Ming Li; Alice Chao; Howard Tang

doi:10.1143/JJAP.43.2302

Electrostatic discharge protection under pad design for copper-low-K VLSI circuits

Jam Wem Lee, Yi-Ming Li^*, Alice Chao, Howard Tang

^*Corresponding author for this work

Institute of Communications Engineering

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

An electrostatic discharge (ESD) under pad structure is proposed and demonstrated for the novel copper-low-K circuit design. By using this approach, the density of both devices and pads could be markedly improved; in a rough estimation, approximately five to twenty percent of the chip area could be saved. Moreover, tests of ESD, latch-up, and bond yield are performed and are found to be better than those of the conventional ones. The designed structure could be considered as a very effective achievement, and this is particularly true for the sub-0.1μm circuit with copper-low-K interconnections.

Original language	English
Pages (from-to)	2302-2305
Number of pages	4
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	43
Issue number	4 B
DOIs	https://doi.org/10.1143/JJAP.43.2302
State	Published - Apr 2004

Keywords

Copper-low K
ESD
Pad density
Protection under pad
Sub-0.1 μm CMOS

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10.1143/JJAP.43.2302

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@article{8aa8c9ee9a22445aa1d1d5fd254b3952,

title = "Electrostatic discharge protection under pad design for copper-low-K VLSI circuits",

abstract = "An electrostatic discharge (ESD) under pad structure is proposed and demonstrated for the novel copper-low-K circuit design. By using this approach, the density of both devices and pads could be markedly improved; in a rough estimation, approximately five to twenty percent of the chip area could be saved. Moreover, tests of ESD, latch-up, and bond yield are performed and are found to be better than those of the conventional ones. The designed structure could be considered as a very effective achievement, and this is particularly true for the sub-0.1μm circuit with copper-low-K interconnections.",

keywords = "Copper-low K, ESD, Pad density, Protection under pad, Sub-0.1 μm CMOS",

author = "Lee, {Jam Wem} and Yi-Ming Li and Alice Chao and Howard Tang",

year = "2004",

month = apr,

doi = "10.1143/JJAP.43.2302",

language = "English",

volume = "43",

pages = "2302--2305",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

number = "4 B",

}

TY - JOUR

T1 - Electrostatic discharge protection under pad design for copper-low-K VLSI circuits

AU - Lee, Jam Wem

AU - Li, Yi-Ming

AU - Chao, Alice

AU - Tang, Howard

PY - 2004/4

Y1 - 2004/4

N2 - An electrostatic discharge (ESD) under pad structure is proposed and demonstrated for the novel copper-low-K circuit design. By using this approach, the density of both devices and pads could be markedly improved; in a rough estimation, approximately five to twenty percent of the chip area could be saved. Moreover, tests of ESD, latch-up, and bond yield are performed and are found to be better than those of the conventional ones. The designed structure could be considered as a very effective achievement, and this is particularly true for the sub-0.1μm circuit with copper-low-K interconnections.

AB - An electrostatic discharge (ESD) under pad structure is proposed and demonstrated for the novel copper-low-K circuit design. By using this approach, the density of both devices and pads could be markedly improved; in a rough estimation, approximately five to twenty percent of the chip area could be saved. Moreover, tests of ESD, latch-up, and bond yield are performed and are found to be better than those of the conventional ones. The designed structure could be considered as a very effective achievement, and this is particularly true for the sub-0.1μm circuit with copper-low-K interconnections.

KW - Copper-low K

KW - ESD

KW - Pad density

KW - Protection under pad

KW - Sub-0.1 μm CMOS

UR - http://www.scopus.com/inward/record.url?scp=3142541131&partnerID=8YFLogxK

U2 - 10.1143/JJAP.43.2302

DO - 10.1143/JJAP.43.2302

M3 - Article

AN - SCOPUS:3142541131

SN - 0021-4922

VL - 43

SP - 2302

EP - 2305

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

IS - 4 B

ER -

Electrostatic discharge protection under pad design for copper-low-K VLSI circuits

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Keywords

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