Electrostatic discharge protection design for high-voltage programming pin in fully-silicided CMOS ICs

Ming-Dou Ker*, Wen Yi Chen, Wuu Trong Shieh, I. Ju Wei

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    2 Scopus citations

    Abstract

    For integrated circuits (ICs) with voltage programming pin (VPP pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the VPP pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to VDD cannot be applied to such VPP pin. In this work, a new ESD protection design is proposed to improve ESD robustness of VPP pin with the consideration of the mistriggering issue when VPP programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.

    Original languageEnglish
    Article number5680922
    Pages (from-to)537-545
    Number of pages9
    JournalIEEE Journal of Solid-State Circuits
    Volume46
    Issue number2
    DOIs
    StatePublished - Feb 2011

    Keywords

    • Electrostatic discharge (ESD)
    • voltage programming pin(V)

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