Electrostatic discharge protection design for high-voltage programming pin in fully-silicided CMOS ICs

Ming-Dou Ker; Wen Yi Chen; Wuu Trong Shieh; I. Ju Wei

doi:10.1109/JSSC.2010.2096114

Electrostatic discharge protection design for high-voltage programming pin in fully-silicided CMOS ICs

Ming-Dou Ker^*, Wen Yi Chen, Wuu Trong Shieh, I. Ju Wei

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

For integrated circuits (ICs) with voltage programming pin (V_PP pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the V_PP pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to VDD cannot be applied to such V_PP pin. In this work, a new ESD protection design is proposed to improve ESD robustness of V_PP pin with the consideration of the mistriggering issue when VPP programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.

Original language	English
Article number	5680922
Pages (from-to)	537-545
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	46
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.2010.2096114
State	Published - 1 Feb 2011

Keywords

Electrostatic discharge (ESD)
voltage programming pin(V)

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10.1109/JSSC.2010.2096114

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title = "Electrostatic discharge protection design for high-voltage programming pin in fully-silicided CMOS ICs",

abstract = "For integrated circuits (ICs) with voltage programming pin (VPP pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the VPP pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to VDD cannot be applied to such VPP pin. In this work, a new ESD protection design is proposed to improve ESD robustness of VPP pin with the consideration of the mistriggering issue when VPP programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.",

keywords = "Electrostatic discharge (ESD), voltage programming pin(V)",

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AU - Ker, Ming-Dou

AU - Chen, Wen Yi

AU - Shieh, Wuu Trong

AU - Wei, I. Ju

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AB - For integrated circuits (ICs) with voltage programming pin (VPP pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the VPP pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to VDD cannot be applied to such VPP pin. In this work, a new ESD protection design is proposed to improve ESD robustness of VPP pin with the consideration of the mistriggering issue when VPP programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.

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KW - voltage programming pin(V)

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Electrostatic discharge protection design for high-voltage programming pin in fully-silicided CMOS ICs

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Keywords

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