For integrated circuits (ICs) with voltage programming pin (VPP pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the VPP pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to VDD cannot be applied to such VPP pin. In this work, a new ESD protection design is proposed to improve ESD robustness of VPP pin with the consideration of the mistriggering issue when VPP programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.
|Number of pages||9|
|Journal||IEEE Journal of Solid-State Circuits|
|State||Published - 1 Feb 2011|
- Electrostatic discharge (ESD)
- voltage programming pin(V)