Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits

Ming-Dou Ker, Hsin Chyh Hsu, Jeng Jie Peng

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations

    Abstract

    A novel electrostatic discharge (ESD) implantation method is proposed to significantly improve machine-model (MM) ESD robustness of NMOS device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300 μm/0.5 μm for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25 μm CMOS process. This ESD implantation method with the n-type impurity is fully process-compatible to general sub-quarter-micron CMOS processes.

    Original languageEnglish
    Title of host publicationProceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003
    PublisherIEEE Computer Society
    Pages363-368
    Number of pages6
    ISBN (Electronic)0769518818
    DOIs
    StatePublished - 1 Jan 2003
    Event2003 4th International Symposium on Quality Electronic Design, ISQED 2003 - San Jose, United States
    Duration: 24 Mar 200326 Mar 2003

    Publication series

    NameProceedings - International Symposium on Quality Electronic Design, ISQED
    Volume2003-January
    ISSN (Print)1948-3287
    ISSN (Electronic)1948-3295

    Conference

    Conference2003 4th International Symposium on Quality Electronic Design, ISQED 2003
    Country/TerritoryUnited States
    CitySan Jose
    Period24/03/0326/03/03

    Keywords

    • CMOS integrated circuits
    • CMOS process
    • Electronic mail
    • Electrostatic discharge
    • Integrated circuit modeling
    • MOS devices
    • Protection
    • Robustness
    • Semiconductor device modeling
    • Stress

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