Electrical performance improvement in SiO2/HfSiO high-k gate stack for advanced low power device application

M. F. Wang; Tuo-Hung Hou; K. L. Mai; P. S. Lim; L. G. Yao; Y. Jin; S. C. Chen; M. S. Liang; W. H. Wu; S. C. Ou; M. C. Chen; T. Y. Huang

doi:10.1109/ICICDT.2004.1309963

Electrical performance improvement in SiO₂/HfSiO high-k gate stack for advanced low power device application

M. F. Wang^*, Tuo-Hung Hou, K. L. Mai, P. S. Lim, L. G. Yao, Y. Jin, S. C. Chen, M. S. Liang, W. H. Wu, S. C. Ou, M. C. Chen, T. Y. Huang

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A study on the impacts of varying base oxide thickness, Si composition and nitridation on HfSiO to the overall high-k gate stack performance was carried out in details. Increasing base oxide thickness from 8A to 12A was found to reduce susceptibility of charge trapping within HfSiO layer and improve drive current. Also, increasing Si composition in HfSiO layer from 50% to 75% produced a higher drive current. However, this improvement was achieved at the expense of a higher gate leakage current. The HfSiO, when subjected to N₂ plasma, forms HfSiON that exhibits excellent high-k dielectric properties with low EOT, low leakage current and high driving current [1][2]. With complete understanding on the contribution from each layer, a good high-k gate stack, based on HfSiON was fabricated. Leakage current was successfully reduced to three orders lower than the conventional SiO₂.

Original language	English
Title of host publication	2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Pages	283-286
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2004.1309963
State	Published - 2004
Event	2004 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States Duration: 17 May 2004 → 20 May 2004

Publication series

Name	2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Conference

Conference	2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Country/Territory	United States
City	Austin, TX
Period	17/05/04 → 20/05/04

Access to Document

10.1109/ICICDT.2004.1309963

Cite this

Wang, M. F., Hou, T.-H., Mai, K. L., Lim, P. S., Yao, L. G., Jin, Y., Chen, S. C., Liang, M. S., Wu, W. H., Ou, S. C., Chen, M. C., & Huang, T. Y. (2004). Electrical performance improvement in SiO₂/HfSiO high-k gate stack for advanced low power device application. In 2004 International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 283-286). (2004 International Conference on Integrated Circuit Design and Technology, ICICDT). https://doi.org/10.1109/ICICDT.2004.1309963

@inproceedings{6d5f12914c224b3a96a9e0385fe403d5,

title = "Electrical performance improvement in SiO2/HfSiO high-k gate stack for advanced low power device application",

abstract = "A study on the impacts of varying base oxide thickness, Si composition and nitridation on HfSiO to the overall high-k gate stack performance was carried out in details. Increasing base oxide thickness from 8A to 12A was found to reduce susceptibility of charge trapping within HfSiO layer and improve drive current. Also, increasing Si composition in HfSiO layer from 50% to 75% produced a higher drive current. However, this improvement was achieved at the expense of a higher gate leakage current. The HfSiO, when subjected to N2 plasma, forms HfSiON that exhibits excellent high-k dielectric properties with low EOT, low leakage current and high driving current [1][2]. With complete understanding on the contribution from each layer, a good high-k gate stack, based on HfSiON was fabricated. Leakage current was successfully reduced to three orders lower than the conventional SiO2.",

author = "Wang, {M. F.} and Tuo-Hung Hou and Mai, {K. L.} and Lim, {P. S.} and Yao, {L. G.} and Y. Jin and Chen, {S. C.} and Liang, {M. S.} and Wu, {W. H.} and Ou, {S. C.} and Chen, {M. C.} and Huang, {T. Y.}",

year = "2004",

doi = "10.1109/ICICDT.2004.1309963",

language = "English",

isbn = "0780385284",

series = "2004 International Conference on Integrated Circuit Design and Technology, ICICDT",

pages = "283--286",

booktitle = "2004 International Conference on Integrated Circuit Design and Technology, ICICDT",

note = "2004 International Conference on Integrated Circuit Design and Technology, ICICDT ; Conference date: 17-05-2004 Through 20-05-2004",

}

Wang, MF, Hou, T-H, Mai, KL, Lim, PS, Yao, LG, Jin, Y, Chen, SC, Liang, MS, Wu, WH, Ou, SC, Chen, MC & Huang, TY 2004, Electrical performance improvement in SiO₂/HfSiO high-k gate stack for advanced low power device application. in 2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004 International Conference on Integrated Circuit Design and Technology, ICICDT, pp. 283-286, 2004 International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, TX, United States, 17/05/04. https://doi.org/10.1109/ICICDT.2004.1309963

Electrical performance improvement in SiO₂/HfSiO high-k gate stack for advanced low power device application. / Wang, M. F.; Hou, Tuo-Hung; Mai, K. L. et al.
2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004. p. 283-286 (2004 International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lim, P. S.

AU - Yao, L. G.

AU - Jin, Y.

AU - Chen, S. C.

AU - Liang, M. S.

AU - Wu, W. H.

AU - Ou, S. C.

AU - Chen, M. C.

AU - Huang, T. Y.

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AB - A study on the impacts of varying base oxide thickness, Si composition and nitridation on HfSiO to the overall high-k gate stack performance was carried out in details. Increasing base oxide thickness from 8A to 12A was found to reduce susceptibility of charge trapping within HfSiO layer and improve drive current. Also, increasing Si composition in HfSiO layer from 50% to 75% produced a higher drive current. However, this improvement was achieved at the expense of a higher gate leakage current. The HfSiO, when subjected to N2 plasma, forms HfSiON that exhibits excellent high-k dielectric properties with low EOT, low leakage current and high driving current [1][2]. With complete understanding on the contribution from each layer, a good high-k gate stack, based on HfSiON was fabricated. Leakage current was successfully reduced to three orders lower than the conventional SiO2.

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BT - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT

T2 - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Y2 - 17 May 2004 through 20 May 2004

ER -

Wang MF, Hou TH, Mai KL, Lim PS, Yao LG, Jin Y et al. Electrical performance improvement in SiO₂/HfSiO high-k gate stack for advanced low power device application. In 2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004. p. 283-286. (2004 International Conference on Integrated Circuit Design and Technology, ICICDT). doi: 10.1109/ICICDT.2004.1309963