Electrical degradation of N-channel poly-Si TFT under AC stress by C-V measurement

Hau Yan Lu*, Po-Tsun Liu, Ting Chang Chang, Sein Chi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The electrical degradation of n-channel poly-silicon thin film transistor (poly-Si TFT) has been investigated under dynamic voltage stress by capacitance-voltage (C-V) measurement. In C-V measurements, the fixed charges in the gate oxide film of TFTs are not affected by the applied small signal, whereas the trap states in the band gap would respond to the applied frequency, so that the dominant degradation mechanism of poly-Si TFTs can be evaluated. Our experimental results show that the degradation of n-type TFTs is caused by additional trap states located at the drain and the source junction in the poly-Si thin film. Furthermore, through the experimental results of the C-V characteristics measured at 10 kHz and 1 MHz, we can infer that the tail states produced by the strained bounding in poly-Si film are mostly responsible for the electrical degradation of n-channel poly-Si TFTs after dynamic stress.

Original languageEnglish
Title of host publicationAD'07 - Proceedings of Asia Display 2007
Pages1184-1189
Number of pages6
StatePublished - Mar 2007
EventAsia Display 2007, AD'07 - Shanghai, China
Duration: 12 Mar 200716 Mar 2007

Publication series

NameAD'07 - Proceedings of Asia Display 2007
Volume2

Conference

ConferenceAsia Display 2007, AD'07
Country/TerritoryChina
CityShanghai
Period12/03/0716/03/07

Keywords

  • AC stress
  • Poly-Si TFT
  • Reliability

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