Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Yi Chieh Tsai, Chia Hsuan Lee, Hsin Chi Chang, Jui Han Liu, Han Wen Hu, Hiroyuki Ito, Young Suk Kim, Takayuki Ohba, Kuan-Neng Chen

Research output: Contribution to journalArticlepeer-review

8 Scopus citations


Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

Original languageEnglish
Pages (from-to)3520-3525
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number7
StateAccepted/In press - 2021


  • 3-D integration
  • bumpless
  • Cleaning
  • Periodic structures
  • Propagation losses
  • Reliability
  • Resistance
  • Stacking
  • through-silicon via (TSV)
  • Through-silicon vias
  • wafer-on-wafer (WOW).


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