Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Yi Chieh Tsai; Chia Hsuan Lee; Hsin Chi Chang; Jui Han Liu; Han Wen Hu; Hiroyuki Ito; Young Suk Kim; Takayuki Ohba; Kuan-Neng Chen

doi:10.1109/TED.2021.3082497

Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Yi Chieh Tsai, Chia Hsuan Lee, Hsin Chi Chang, Jui Han Liu, Han Wen Hu, Hiroyuki Ito, Young Suk Kim, Takayuki Ohba, Kuan-Neng Chen

Research output: Contribution to journal › Article › peer-review

11 Scopus citations

Abstract

Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

Original language	English
Article number	9444571
Pages (from-to)	3520-3525
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	68
Issue number	7
DOIs	https://doi.org/10.1109/TED.2021.3082497
State	Published - Jul 2021

Keywords

3-D integration
bumpless
through-silicon via (TSV)
wafer-on-wafer (WOW)

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title = "Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via",

abstract = "Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.",

keywords = "3-D integration, bumpless, through-silicon via (TSV), wafer-on-wafer (WOW)",

author = "Tsai, {Yi Chieh} and Lee, {Chia Hsuan} and Chang, {Hsin Chi} and Liu, {Jui Han} and Hu, {Han Wen} and Hiroyuki Ito and Kim, {Young Suk} and Takayuki Ohba and Kuan-Neng Chen",

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doi = "10.1109/TED.2021.3082497",

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AU - Tsai, Yi Chieh

AU - Lee, Chia Hsuan

AU - Chang, Hsin Chi

AU - Liu, Jui Han

AU - Hu, Han Wen

AU - Ito, Hiroyuki

AU - Kim, Young Suk

AU - Ohba, Takayuki

AU - Chen, Kuan-Neng

N1 - Publisher Copyright: IEEE

PY - 2021/7

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N2 - Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

AB - Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

KW - 3-D integration

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Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

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Keywords

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