Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

Sheng Chia Hsu, Yiming Li*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

In this work, we study the impact of random interface traps (RITs) at the interface of SiOx/Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state (Dit). The variability of the off-state current (Ioff) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high Dit varying from 5 × 1012 to 5 × 1013 eV−1 cm−2 owing to significant threshold voltage (Vth) fluctuation. The results of this study indicate that if the level of Dit is lower than 1 × 1012 eV−1 cm−2, the normalized variability of the on-state current, Ioff, Vth, DIBL, and subthreshold swing is within 5%.

Original languageEnglish
Article number633
JournalNanoscale Research Letters
Volume9
Issue number1
DOIs
StatePublished - 1 Dec 2014

Keywords

  • Bulk FinFETs
  • Density of interface traps
  • Electrical characteristic fluctuation
  • Interface trap fluctuation
  • Random interface traps
  • Statistical device simulation

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