Efficient write scheme for algorithm-based multi-ported memory

Bo Ya Chen; Bo En Cher; Bo Cheng Lai

doi:10.1109/VLSI-DAT.2019.8741927

Efficient write scheme for algorithm-based multi-ported memory

Bo Ya Chen, Bo En Cher, Bo Cheng Lai

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.

Original language	English
Title of host publication	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728106557
DOIs	https://doi.org/10.1109/VLSI-DAT.2019.8741927
State	Published - Apr 2019
Event	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan Duration: 22 Apr 2019 → 25 Apr 2019

Publication series

Name	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/19 → 25/04/19

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10.1109/VLSI-DAT.2019.8741927

Cite this

Chen, B. Y., Cher, B. E., & Lai, B. C. (2019). Efficient write scheme for algorithm-based multi-ported memory. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 [8741927] (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741927

@inproceedings{6edd0b3656184733879fb721fe11d6b0,

title = "Efficient write scheme for algorithm-based multi-ported memory",

abstract = "This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.",

author = "Chen, {Bo Ya} and Cher, {Bo En} and Lai, {Bo Cheng}",

year = "2019",

month = apr,

doi = "10.1109/VLSI-DAT.2019.8741927",

language = "English",

series = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

address = "United States",

note = "null ; Conference date: 22-04-2019 Through 25-04-2019",

}

Chen, BY, Cher, BE & Lai, BC 2019, Efficient write scheme for algorithm-based multi-ported memory. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741927, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 22/04/19. https://doi.org/10.1109/VLSI-DAT.2019.8741927

Efficient write scheme for algorithm-based multi-ported memory. / Chen, Bo Ya; Cher, Bo En; Lai, Bo Cheng.

2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741927 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Efficient write scheme for algorithm-based multi-ported memory

AU - Chen, Bo Ya

AU - Cher, Bo En

AU - Lai, Bo Cheng

PY - 2019/4

Y1 - 2019/4

N2 - This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.

AB - This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.

UR - http://www.scopus.com/inward/record.url?scp=85068606231&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2019.8741927

DO - 10.1109/VLSI-DAT.2019.8741927

M3 - Conference contribution

AN - SCOPUS:85068606231

T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 22 April 2019 through 25 April 2019

ER -

Efficient write scheme for algorithm-based multi-ported memory

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