Efficient strategies of compressing three-dimensional sparse arrays based on Intel XEON and Intel XEON Phi environments

Chun Yuan Lin, Huang Ting Yen, Che Lun Hung*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Array operations are useful in a lot of important scientific codes, such as molecular dynamics, finite-element methods, atmosphere and ocean sciences, and etc. In recent years, more and more applications, such as geological analysis and medical images processing, are solved and processed by using array operations for three-dimensional (abbreviate to 3D) sparse arrays. Due to the huge computation time, it is necessary to compress the sparse arrays to compact structures in order to avoid unnecessary computations. Parallel processing is also a suitable solution to speed up the array operations based on multiprocessors, multicomputers and accelerators. How to compress the sparse arrays efficiently is the first task of designing parallel algorithms for practical applications with sparse array operations. Hence, efficient strategies of compressing 3D sparse arrays based on Intel XEON (multiprocessor) and Intel XEON Phi (accelerator) environments are proposed in this paper. For each environment, two strategies, inter-task parallelization and intra-task parallelization, are presented to compress a series of sparse arrays and single large sparse array, respectively. From experimental results, the inter-task parallelization strategy achieves 16x and 18x speedup ratios based on Intel XEON E5-2670 v2 and Intel Xeon Phi SE10X, respectively; 4x and 5x speedup ratios, respectively, for the intra-task parallelization strategy.

Original languageEnglish
Title of host publicationProceedings - 15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015
EditorsLuigi Atzori, Xiaolong Jin, Stephen Jarvis, Lei Liu, Ramon Aguero Calvo, Jia Hu, Geyong Min, Nektarios Georgalas, Yulei Wu
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1383-1388
Number of pages6
ISBN (Electronic)9781509001545
DOIs
StatePublished - 22 Dec 2015
Event15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015 - Liverpool, United Kingdom
Duration: 26 Oct 201528 Oct 2015

Publication series

NameProceedings - 15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015

Conference

Conference15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015
Country/TerritoryUnited Kingdom
CityLiverpool
Period26/10/1528/10/15

Keywords

  • Accelerator
  • Array operation
  • Data compression method
  • Intel XEON
  • Intel XEON Phi
  • Multicomputer
  • Multiprocessor
  • Parallel processing

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