Efficient hardware architecture of η_T pairing accelerator over characteristic three

Keyphrases

• Efficient Hardware Architecture 100%
• Miller Loop 100%
• Bilinear Pairing Computation 100%
• Characteristic 3 100%
• Area-time Product 100%
• Final Exponentiation 100%
• 90-nm CMOS Technology 50%
• Computation Cost 50%
• Parallelization 50%
• Cloud Computing 50%
• Multiplier Design 50%
• Critical Path Delay 50%
• Torus 50%
• Hardware-software Co-design 50%
• High Security 50%
• Hardware Scheduling 50%
• Fully pipelined 50%
• Mathematical Manipulation 50%
• Secure Pairing 50%
• Pairing-based 50%
• Frobenius Map 50%
• Co-design Method 50%

Computer Science

• Hardware Architecture 100%
• bilinear map 100%
• Computer Hardware 100%
• Pipelining 50%
• Computation Cost 50%
• Efficient Algorithm 50%
• Datapath 50%
• Clock Cycle 50%
• Critical Path Delay 50%
• Parallelization 50%
• Cloud Computing 50%

Engineering

• Clock Cycle 100%
• Critical Path 100%
• Cloud Computing 100%