Abstract
The linear discriminant function classifier is a widely used but computationally demanding method in statistical pattern recognition. This paper describes a bit-level systolic array for the linear discriminant function classifier to improve its processing speed. The system includes a new scheme for inner product computation, which not only has 100% efficiency but also gains a speed improvement over a previous method, and yields classification results at an average rate of one per B cycles of the array, where B is the wordlength of the input data. The throughput is higher than those of the related bit level arrays described previously.
Original language | English |
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Pages (from-to) | 216-224 |
Number of pages | 9 |
Journal | IEE Proceedings G: Electronics Circuits and Systems |
Volume | 134 |
Issue number | 5 |
DOIs | |
State | Published - Oct 1987 |
Keywords
- Array processing
- Circuit eory and design
- Mathematical techniques
- Pattern recognition