TY - GEN
T1 - Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization
AU - Li, Bo Han
AU - Lin, Kuan Chih
AU - Zuo, Hao
AU - Pan, Po Cheng
AU - Chen, Hung Ming
AU - Jou, Shyh Jye
AU - Liu, Chien Nan Jimmy
AU - Lai, Bo Cheng
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This study introduces a pioneering method for the layout generation of analog circuits, specifically designed for RRAM computing circuits using the TSMC 40nm process. By focusing on area and wire optimization, we have managed to reduce the layout area by up to 28.6% and the wirelength by 45.3%, all while maintaining power consumption and accuracy at levels comparable to conventional approaches. The method leverages strategic guard ring placement and precise transistor spacing to optimize the layout efficiently. Our findings highlight the method's capacity to address the challenges in analog layout generation, offering a pathway to enhance memory computing systems. This work contributes to the broader field of computing circuit design, providing insights that could influence future approaches on RRAM compatible physical designs.
AB - This study introduces a pioneering method for the layout generation of analog circuits, specifically designed for RRAM computing circuits using the TSMC 40nm process. By focusing on area and wire optimization, we have managed to reduce the layout area by up to 28.6% and the wirelength by 45.3%, all while maintaining power consumption and accuracy at levels comparable to conventional approaches. The method leverages strategic guard ring placement and precise transistor spacing to optimize the layout efficiently. Our findings highlight the method's capacity to address the challenges in analog layout generation, offering a pathway to enhance memory computing systems. This work contributes to the broader field of computing circuit design, providing insights that could influence future approaches on RRAM compatible physical designs.
UR - http://www.scopus.com/inward/record.url?scp=85204977789&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS60917.2024.10658764
DO - 10.1109/MWSCAS60917.2024.10658764
M3 - Conference contribution
AN - SCOPUS:85204977789
T3 - Midwest Symposium on Circuits and Systems
SP - 1085
EP - 1090
BT - 2024 IEEE 67th International Midwest Symposium on Circuits and Systems, MWSCAS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 67th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2024
Y2 - 11 August 2024 through 14 August 2024
ER -