Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Po Jung Sung; Chun-Jung Su; Shih Hsuan Lo; Fu Kuo Hsueh; Darsen D. Lu; Yao Jen Lee; Tien-Sheng Chao

doi:10.1109/JEDS.2020.2987005

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Po Jung Sung, Chun-Jung Su, Shih Hsuan Lo, Fu Kuo Hsueh, Darsen D. Lu, Yao Jen Lee^*, Tien-Sheng Chao

^*Corresponding author for this work

Department of Electrophysics

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I_D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I_d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V_D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

Original language	English
Article number	9063644
Pages (from-to)	474-480
Number of pages	7
Journal	IEEE Journal of the Electron Devices Society
Volume	8
DOIs	https://doi.org/10.1109/JEDS.2020.2987005
State	Published - 13 Apr 2020

Keywords

FeFET
ferroelectric
forming gas annealing (FGA)
HfZrO
steep slop

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10.1109/JEDS.2020.2987005

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title = "Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter",

abstract = "In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.",

keywords = "FeFET, ferroelectric, forming gas annealing (FGA), HfZrO, steep slop",

author = "Sung, {Po Jung} and Chun-Jung Su and Lo, {Shih Hsuan} and Hsueh, {Fu Kuo} and Lu, {Darsen D.} and Lee, {Yao Jen} and Tien-Sheng Chao",

year = "2020",

month = apr,

day = "13",

doi = "10.1109/JEDS.2020.2987005",

language = "English",

volume = "8",

pages = "474--480",

journal = "IEEE Journal of the Electron Devices Society",

issn = "2168-6734",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

AU - Sung, Po Jung

AU - Su, Chun-Jung

AU - Lo, Shih Hsuan

AU - Hsueh, Fu Kuo

AU - Lu, Darsen D.

AU - Lee, Yao Jen

AU - Chao, Tien-Sheng

PY - 2020/4/13

Y1 - 2020/4/13

N2 - In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

AB - In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

KW - FeFET

KW - ferroelectric

KW - forming gas annealing (FGA)

KW - HfZrO

KW - steep slop

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DO - 10.1109/JEDS.2020.2987005

M3 - Article

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SP - 474

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JO - IEEE Journal of the Electron Devices Society

JF - IEEE Journal of the Electron Devices Society

M1 - 9063644

ER -

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

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