Effective error diagnosis for RTL designs in HDLs

Tai Ying Jiang, Chien-Nan Liu, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in. The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate.

Original languageEnglish
Title of host publicationProceedings of the 11th Asian Test Symposium, ATS 2002
PublisherIEEE Computer Society
Pages362-367
Number of pages6
ISBN (Electronic)0769518257, 0769518257
DOIs
StatePublished - 1 Jan 2002
Event11th Asian Test Symposium, ATS 2002 - Guam, United States
Duration: 18 Nov 200220 Nov 2002

Publication series

NameProceedings of the Asian Test Symposium
Volume2002-January
ISSN (Print)1081-7735

Conference

Conference11th Asian Test Symposium, ATS 2002
Country/TerritoryUnited States
CityGuam
Period18/11/0220/11/02

Keywords

  • Boolean functions
  • Circuit simulation
  • Circuit synthesis
  • Design engineering
  • Electronic equipment testing
  • Error correction
  • Hardware design languages
  • Process design
  • State estimation
  • Very large scale integration

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