Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

Shen Yang Lee; Han Wei Chen; Chiuan Huei Shen; Po Yi Kuo; Chun Chih Chung; Yu En Huang; Hsin Yu Chen; Tien Sheng Chao

doi:10.1109/TED.2019.2958350

Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

Shen Yang Lee, Han Wei Chen, Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Yu En Huang, Hsin Yu Chen, Tien Sheng Chao^*

^*Corresponding author for this work

Department of Electrophysics

Research output: Contribution to journal › Article › peer-review

24 Scopus citations

Abstract

In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO₂ seed layer, Hf_1-x Zr_xO₂ in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.

Original language	English
Article number	8951114
Pages (from-to)	711-716
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	67
Issue number	2
DOIs	https://doi.org/10.1109/TED.2019.2958350
State	Published - Feb 2020

Keywords

Gate-all-around (GAA)
Hf1O (HZO)
nanowire (NW)
negative capacitance (NC)
negative differential resistance (NDR)
negative drain-induced barrier lowering (DIBL)
ZrO

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Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y., & Chao, T. S. (2020). Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs. IEEE Transactions on Electron Devices, 67(2), 711-716. Article 8951114. https://doi.org/10.1109/TED.2019.2958350

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title = "Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs",

abstract = "In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf1-x ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.",

keywords = "Gate-all-around (GAA), Hf1O (HZO), nanowire (NW), negative capacitance (NC), negative differential resistance (NDR), negative drain-induced barrier lowering (DIBL), ZrO",

author = "Lee, {Shen Yang} and Chen, {Han Wei} and Shen, {Chiuan Huei} and Kuo, {Po Yi} and Chung, {Chun Chih} and Huang, {Yu En} and Chen, {Hsin Yu} and Chao, {Tien Sheng}",

year = "2020",

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doi = "10.1109/TED.2019.2958350",

language = "English",

volume = "67",

pages = "711--716",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T2 - Planar Capacitors to 3-D FETs

AU - Lee, Shen Yang

AU - Chen, Han Wei

AU - Shen, Chiuan Huei

AU - Kuo, Po Yi

AU - Chung, Chun Chih

AU - Huang, Yu En

AU - Chen, Hsin Yu

AU - Chao, Tien Sheng

PY - 2020/2

Y1 - 2020/2

N2 - In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf1-x ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.

AB - In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf1-x ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.

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KW - negative differential resistance (NDR)

KW - negative drain-induced barrier lowering (DIBL)

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JF - IEEE Transactions on Electron Devices

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ER -

Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

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Keywords

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