Early-late gate receiving for Bluetooth packet

C. S. Peng; M. H. Chang; Kuei-Ann Wen

doi:10.1109/VTSA.2001.934482

Early-late gate receiving for Bluetooth packet

C. S. Peng^*, M. H. Chang, Kuei-Ann Wen

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analogto-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.

Original language	English
Pages	57-60
Number of pages	4
DOIs	https://doi.org/10.1109/VTSA.2001.934482
State	Published - 18 Apr 2001
Event	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan Duration: 18 Apr 2001 → 20 Apr 2001

Conference

Conference	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Country/Territory	Taiwan
City	Hsinchu
Period	18/04/01 → 20/04/01

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10.1109/VTSA.2001.934482

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@conference{561d5a3b3b4b4ba193b6107822212536,

title = "Early-late gate receiving for Bluetooth packet",

abstract = "An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analogto-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.",

author = "Peng, {C. S.} and Chang, {M. H.} and Kuei-Ann Wen",

year = "2001",

month = apr,

day = "18",

doi = "10.1109/VTSA.2001.934482",

language = "English",

pages = "57--60",

note = "2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings ; Conference date: 18-04-2001 Through 20-04-2001",

}

TY - CONF

T1 - Early-late gate receiving for Bluetooth packet

AU - Peng, C. S.

AU - Chang, M. H.

AU - Wen, Kuei-Ann

PY - 2001/4/18

Y1 - 2001/4/18

N2 - An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analogto-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.

AB - An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analogto-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.

UR - http://www.scopus.com/inward/record.url?scp=0034849192&partnerID=8YFLogxK

U2 - 10.1109/VTSA.2001.934482

DO - 10.1109/VTSA.2001.934482

M3 - Paper

AN - SCOPUS:0034849192

SP - 57

EP - 60

T2 - 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Y2 - 18 April 2001 through 20 April 2001

ER -

Early-late gate receiving for Bluetooth packet

Abstract

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