A dynamic-floating-gate design is proposed to improve ESD robustness of the driving-current-programmable CMOS output buffers in a 0.35-μm CMOS cell library. Through suitable design to dynamically float the gates of the output NMOS/PMOS which are originally unused in a 2-mA output buffer, the ND-mode (PS-mode) ESD level of the 2-mA output buffer can be improved from the original 1.5 KV (1.0 KV) up to greater than 8 KV.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1998|
|Event||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
Duration: 31 May 1998 → 3 Jun 1998