TY - JOUR

T1 - Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series

AU - He, Wen Quan

AU - Chen, Yuan Ho

AU - Jou, Shyh-Jye

N1 - Publisher Copyright:
© 2015, Springer Science+Business Media New York.

PY - 2016/8/1

Y1 - 2016/8/1

N2 - This paper proposes a dynamic error-compensated circuit for a fixed-width Booth multiplier based on the conditional probability of input series (CPIS), which enables high-speed operation and low circuit overhead. The dynamic compensated value is produced directly from the multiplier of input series simultaneously with the Booth encoder and therefore does not affect the critical path. The compensated formula is derived using a mathematical probability model, rather than time-consuming simulation. This formula is a function of bit-length of the multiplier; thus, the compensated circuit is easily implemented for bit-length of 32, 64, or longer. Accuracy-efficiency, which indicates the signal-to-noise ratio per unit area and unit delay, is included for ease of comparison. Compared with previous works, the greatest advantage of the proposed CPIS is high speed. Furthermore, the proposed CPIS achieves higher accuracy-efficiency. Implemented using the TSMC 0.18-μ m CMOS process, the proposed 32-bit Booth multiplier has an operation frequency of 50 MHz with power consumption of 7.3 mW.

AB - This paper proposes a dynamic error-compensated circuit for a fixed-width Booth multiplier based on the conditional probability of input series (CPIS), which enables high-speed operation and low circuit overhead. The dynamic compensated value is produced directly from the multiplier of input series simultaneously with the Booth encoder and therefore does not affect the critical path. The compensated formula is derived using a mathematical probability model, rather than time-consuming simulation. This formula is a function of bit-length of the multiplier; thus, the compensated circuit is easily implemented for bit-length of 32, 64, or longer. Accuracy-efficiency, which indicates the signal-to-noise ratio per unit area and unit delay, is included for ease of comparison. Compared with previous works, the greatest advantage of the proposed CPIS is high speed. Furthermore, the proposed CPIS achieves higher accuracy-efficiency. Implemented using the TSMC 0.18-μ m CMOS process, the proposed 32-bit Booth multiplier has an operation frequency of 50 MHz with power consumption of 7.3 mW.

KW - Booth encoder

KW - Dynamic error compensation

KW - Fixed-width multiplier

KW - Mathematical probable model

UR - http://www.scopus.com/inward/record.url?scp=84975263531&partnerID=8YFLogxK

U2 - 10.1007/s00034-015-0186-2

DO - 10.1007/s00034-015-0186-2

M3 - Article

AN - SCOPUS:84975263531

SN - 0278-081X

VL - 35

SP - 2972

EP - 2991

JO - Circuits, Systems, and Signal Processing

JF - Circuits, Systems, and Signal Processing

IS - 8

ER -