DVFS binning using machine-learning techniques

Keng Wei Chang, Chun Yang Huang, Szu Pang Mu, Jian Min Huang, Shi Hao Chen, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations


This paper presents a framework which can avoid the lengthy system test by utilizing machine-learning techniques to classify parts into different DVFS bins based on the results collected at CP and FT test only. The core machine-learning techniques in use are Bayesian linear regression for model fitting and stepwise regression for feature selection. Another method, called the incremental F-max-model search, is also presented to reduce the test time of collecting the required data for each training sample. The experiments are conducted based on 249 test chips of an industrial SoC. The experimental results demonstrate that our proposed framework can achieve a high accuracy ratio of placing a part into correct DVFS bin without placing any slower part into a faster DVFS bin. The experimental results also demonstrate that the incremental F-max-model search can save 45.1% and 52.6% of applications of the system-level test compared to the conventional median linear search and binary search, respectively.

Original languageEnglish
Title of host publicationProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)9781538651803
StatePublished - 11 Sep 2018
Event2nd IEEE International Test Conference in Asia, ITC-Asia 2018 - Harbin, China
Duration: 15 Aug 201817 Aug 2018

Publication series

NameProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018


Conference2nd IEEE International Test Conference in Asia, ITC-Asia 2018


  • Binning
  • DVFS
  • Machine learning
  • System Fmax


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