Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

Hsin Chyh Hsu; Ming-Dou Ker

doi:10.1109/ISQED.2006.54

Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

Hsin Chyh Hsu, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 /spl mu/m/0.18 /spl mu/m) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products.

Original language	English
Title of host publication	Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
Pages	503-506
Number of pages	4
DOIs	https://doi.org/10.1109/ISQED.2006.54
State	Published - 1 Dec 2006
Event	7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States Duration: 27 Mar 2006 → 29 Mar 2006

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	7th International Symposium on Quality Electronic Design, ISQED 2006
Country/Territory	United States
City	San Jose, CA
Period	27/03/06 → 29/03/06

Access to Document

10.1109/ISQED.2006.54

Cite this

Hsu, H. C., & Ker, M.-D. (2006). Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask. In Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006 (pp. 503-506). Article 1613186 (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2006.54

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title = "Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask",

abstract = "NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 /spl mu/m/0.18 /spl mu/m) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products.",

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Hsu, HC & Ker, M-D 2006, Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask. in Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006., 1613186, Proceedings - International Symposium on Quality Electronic Design, ISQED, pp. 503-506, 7th International Symposium on Quality Electronic Design, ISQED 2006, San Jose, CA, United States, 27/03/06. https://doi.org/10.1109/ISQED.2006.54

Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask. / Hsu, Hsin Chyh; Ker, Ming-Dou.
Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006. 2006. p. 503-506 1613186 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

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