Distributed Sorting Architecture on Multiple FPGA

Yi Da Hsin, Yen Shi Kuo, Bo Cheng Lai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

FPGA has demonstrated promising performance in high throughput data sorting. Data compression techniques are adopted to exploit the redundant information between subsequent values in a sorted dataset. However, the standalone FPGA design inhibits the scalability to handle the growing dataset. Moreover, previous data compression techniques in data sorting lack versatility to support various ranges of data. This paper proposes the design of a distributed sorting accelerator on multiple FPGAs and introduce a Configurable Compressed Array to handle the various data widths. The experimental results have shown that the proposed design attains 3.69x enhancement when compared to the previous design.

Original languageEnglish
Title of host publication2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665409216
DOIs
StatePublished - 2022
Event2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, Taiwan
Duration: 18 Apr 202221 Apr 2022

Publication series

Name2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
Country/TerritoryTaiwan
CityHsinchu
Period18/04/2221/04/22

Keywords

  • big data
  • compression technique
  • distributed computing architecture
  • FPGA
  • sort

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