Discrete dopant fluctuated 20nm/15nm-gate planar CMOS

Fu Liang Yang*, Jiunn Ren Hwang, Hung Ming Chen, Jeng Jung Shen, Shao Ming Yu, Yiming Li, Denny D. Tang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

16 Scopus citations

Abstract

We have, for the first time, experimentally quantified random dopant distribution (RDD) induced Vt standard deviation up to 4OmV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V, variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.

Original languageEnglish
Article number4339695
Pages (from-to)208-209
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 12 Jun 2007
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: 12 Jun 200714 Jun 2007

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