Digitally programmable DC-DC voltage down converter

M. C. Lin; H. Y. Lin; C. L. Chen; Shyh-Jye Jou

doi:10.1109/APASIC.1999.824109

Digitally programmable DC-DC voltage down converter

M. C. Lin, H. Y. Lin, C. L. Chen, Shyh-Jye Jou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-μm triple-metal CMOS process on 1000×1000 μm ² core size. The simulation results show that it can convert +5 V input voltage to +2∼+5 V output voltage in the 50 μs settling time.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	367-370
Number of pages	4
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824109
State	Published - 1 Jan 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 23 Aug 1999 → 25 Aug 1999

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	23/08/99 → 25/08/99

Access to Document

10.1109/APASIC.1999.824109

Cite this

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title = "Digitally programmable DC-DC voltage down converter",

abstract = " This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-μm triple-metal CMOS process on 1000×1000 μm 2 core size. The simulation results show that it can convert +5 V input voltage to +2∼+5 V output voltage in the 50 μs settling time. ",

author = "Lin, {M. C.} and Lin, {H. Y.} and Chen, {C. L.} and Shyh-Jye Jou",

year = "1999",

month = jan,

day = "1",

doi = "10.1109/APASIC.1999.824109",

language = "English",

isbn = "0780357051",

series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "367--370",

booktitle = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

address = "美國",

note = "1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",

}

Lin, MC, Lin, HY, Chen, CL & Jou, S-J 1999, Digitally programmable DC-DC voltage down converter. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824109, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 367-370, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 23/08/99. https://doi.org/10.1109/APASIC.1999.824109

Digitally programmable DC-DC voltage down converter. / Lin, M. C.; Lin, H. Y.; Chen, C. L. et al.
AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 367-370 824109 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Digitally programmable DC-DC voltage down converter

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AU - Lin, H. Y.

AU - Chen, C. L.

AU - Jou, Shyh-Jye

PY - 1999/1/1

Y1 - 1999/1/1

N2 - This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-μm triple-metal CMOS process on 1000×1000 μm 2 core size. The simulation results show that it can convert +5 V input voltage to +2∼+5 V output voltage in the 50 μs settling time.

AB - This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-μm triple-metal CMOS process on 1000×1000 μm 2 core size. The simulation results show that it can convert +5 V input voltage to +2∼+5 V output voltage in the 50 μs settling time.

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BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999

Y2 - 23 August 1999 through 25 August 1999

ER -

Digitally programmable DC-DC voltage down converter

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