Digital Buck Converter with Switching Loss Reduction Scheme for Light Load Efficiency Enhancement

Chung Shiang Wu, Hui Hsuan Lee, Po-Hung Chen, Wei Hwang

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

In this brief, we present a digital pulsewidth modulation buck converter with a switching loss reduction scheme to improve conversion efficiency at light load conditions. The proposed switching loss reduction scheme combines power-stage voltage swing scaling, transistor width scaling, and controller voltage scaling to reduce the dynamic power dissipation of the system. The power-stage voltage swing scaling also reduces the inductor current ripple at light load conditions, which extends the available output current range in the continuous conduction mode (CCM). A duty ratio estimation mechanism is implemented to provide a modulated signal with the correct duty ratio to control the output voltage. Experimental results demonstrate a 38% conversion efficiency improvement at a 50-$\mu \text{A}$ output current. In addition, the proposed circuit achieves a 96% peak efficiency with an output current ranging from 20 $\mu \text{A}$ to 30 mA in the CCM operation.

Original languageEnglish
Article number7527660
Pages (from-to)783-787
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number2
DOIs
StatePublished - 1 Feb 2017

Keywords

  • Controller voltage scaling
  • digital buck converter
  • power-stage voltage swing scaling
  • Switching loss reduction

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