DiffServ over network processors: Implementation and evaluation

Ying-Dar Lin, Yi Neng Lin, Shun Chin Yang, Yu Sheng Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations


Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data-plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that though the system can scale to wire-speed of 1.8 Gbps in simple IP forwarding, the throughput declines to 180 Mbpssim/290 Mbps when DiffServ is performed due to the double bottlenecks of SRAM and microengines. Through internal benchmarks, the performance bottleneck was found to be able to shift from one place to another given different network services and algorithms. Most of the result reported here remain the same for other NPs since they have similar architectures and components.

Original languageEnglish
Title of host publicationProceedings - 10th Symposium on High Performance Interconnects, HOTI 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)0769516505
StatePublished - 2002
Event10th Symposium on High Performance Interconnects, HOTI 2002 - Stanford, United States
Duration: 21 Aug 200223 Aug 2002

Publication series

NameProceedings - Symposium on the High Performance Interconnects, Hot Interconnects
ISSN (Print)1550-4794


Conference10th Symposium on High Performance Interconnects, HOTI 2002
Country/TerritoryUnited States


  • Acceleration
  • Communication system traffic control
  • Computer networks
  • Coprocessors
  • Diffserv networks
  • Hardware
  • Random access memory
  • Scalability
  • Switches
  • Throughput


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