Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

K. Y. Hsiang, C. Y. Liao, J. H. Liu, C. Y. Lin, J. Y. Lee, Z. F. Lou, F. S. Chang, W. C. Ray, Z. X. Li, H. C. Tseng, C. C. Wang, M. H. Liao, T. H. Hou, M. H. Lee^*

^*Corresponding author for this work