Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

K. Y. Hsiang; C. Y. Liao; J. H. Liu; C. Y. Lin; J. Y. Lee; Z. F. Lou; F. S. Chang; W. C. Ray; Z. X. Li; H. C. Tseng; C. C. Wang; M. H. Liao; T. H. Hou; M. H. Lee

doi:10.1109/LED.2022.3204445

Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

K. Y. Hsiang, C. Y. Liao, J. H. Liu, C. Y. Lin, J. Y. Lee, Z. F. Lou, F. S. Chang, W. C. Ray, Z. X. Li, H. C. Tseng, C. C. Wang, M. H. Liao, T. H. Hou, M. H. Lee

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf_1-xZr_xO₂ (HZO) and Al₂O₃ has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al₂O₃ 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.

Original language	English
Pages (from-to)	1
Number of pages	1
Journal	Ieee Electron Device Letters
DOIs	https://doi.org/10.1109/LED.2022.3204445
State	Accepted/In press - 2022

Keywords

Antiferroelectric
Computer architecture
Ferroelectric
HfZrO2
Iron
Resistance
Resistors
Three-dimensional displays
Tunneling
Voltage

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10.1109/LED.2022.3204445

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Hsiang, K. Y., Liao, C. Y., Liu, J. H., Lin, C. Y., Lee, J. Y., Lou, Z. F., Chang, F. S., Ray, W. C., Li, Z. X., Tseng, H. C., Wang, C. C., Liao, M. H., Hou, T. H., & Lee, M. H. (Accepted/In press). Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture. Ieee Electron Device Letters, 1. https://doi.org/10.1109/LED.2022.3204445

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title = "Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture",

abstract = "The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf1-xZrxO2 (HZO) and Al2O3 has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al2O3 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.",

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author = "Hsiang, {K. Y.} and Liao, {C. Y.} and Liu, {J. H.} and Lin, {C. Y.} and Lee, {J. Y.} and Lou, {Z. F.} and Chang, {F. S.} and Ray, {W. C.} and Li, {Z. X.} and Tseng, {H. C.} and Wang, {C. C.} and Liao, {M. H.} and Hou, {T. H.} and Lee, {M. H.}",

note = "Publisher Copyright: IEEE",

year = "2022",

doi = "10.1109/LED.2022.3204445",

language = "English",

pages = "1",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

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T1 - Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

AU - Hsiang, K. Y.

AU - Liao, C. Y.

AU - Liu, J. H.

AU - Lin, C. Y.

AU - Lee, J. Y.

AU - Lou, Z. F.

AU - Chang, F. S.

AU - Ray, W. C.

AU - Li, Z. X.

AU - Tseng, H. C.

AU - Wang, C. C.

AU - Liao, M. H.

AU - Hou, T. H.

AU - Lee, M. H.

N1 - Publisher Copyright: IEEE

PY - 2022

Y1 - 2022

N2 - The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf1-xZrxO2 (HZO) and Al2O3 has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al2O3 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.

AB - The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) Hf1-xZrxO2 (HZO) and Al2O3 has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al2O3 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.

KW - Antiferroelectric

KW - Computer architecture

KW - Ferroelectric

KW - HfZrO2

KW - Iron

KW - Resistance

KW - Resistors

KW - Three-dimensional displays

KW - Tunneling

KW - Voltage

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U2 - 10.1109/LED.2022.3204445

DO - 10.1109/LED.2022.3204445

M3 - Article

AN - SCOPUS:85137892974

SN - 0741-3106

SP - 1

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

ER -

Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

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Keywords

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